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1 ? fn7467.7 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright intersil americas inc. 2004-2009, 2011. all rights reserved all other trademarks mentioned are the property of their respective owners. el8188 micropower single s upply rail-to-rail input-output precision op amp the el8188 is a precision low power, operational amplifier. the device is optimized for single supply operation between 2.4v to 5.5v. this enables operation from one lithium cell or two ni-cd batteries. the input range includes both positive and negative rail. the el8188 draws minimal supply current (55a) while meeting excellent dc-accuracy, noise, and output drive specifications. features ? typical 55a supply current ? 1mv max offset voltage ? typical 1pa input bias current ? 266khz gain-bandwidth product ? single supply operation between 2.4v to 5.5v ? rail-to-rail input and output ? ground sensing ? output sources and sinks 26ma load current ? pb-free (rohs compliant) applications ? battery - or solar-powered systems ? 4ma to 20ma current loops ? handheld consumer products ? medical devices ? thermocouple amplifiers ? photodiode pre-amps ? ph probe amplifiers ordering information part number part marking temp range (c) package (pb-free) pkg. dwg. # el8188fiz-t7* (note 2) 188z -40 to +125 6 ld wlcsp (1.5mmx1.0mm) w3x2.6c EL8188FWZ-T7a* (notes 1, 3) bbya -40 to +125 6 ld sot-23 p6.064a EL8188FWZ-T7* (notes 1, 3) bbya -40 to +125 6 ld sot-23 p6.064a el8188isz (note 1) 8188isz -40 to +125 8 ld soic m8.15e el8188isz-t7* (note 1) 8188isz -40 to +125 8 ld soic m8.15e el8188isz-t13* (note 1) 8188isz -40 to +125 8 ld soic m8.15e *please refer to tb347 for details on reel specifications. notes: 1. these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb- free requirements of ipc/jedec j std-020 2. these intersil pb-free wlcsp and bga packaged products products employ special pb-free material sets; molding compounds/die attach materials and snagcu - e1 solder ball terminals, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free wlcsp and bga packaged products are ms l classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. the part marking is located on the bottom of the part. pinouts el8188 (6 ld sot-23) top view el8188 (8 ld so) top view el8188 (6 ld wlcsp) top view 1 2 3 6 4 5 +- out v- in+ v+ dnc in- 1 2 3 4 8 7 6 5 - + dnc in- in+ dnc v+ out v- dnc 2 1 a b c out v- in+ dnc v+ in- data sheet february 24, 2011 f o r a p o s s i b l e s u b s t i t u t e p r o d u c t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c o b s o l e t e p r o d u c t
2 fn7467.7 february 24, 2011 absolute maxi mum ratings (t a = +25c) thermal information supply voltage (v s ) and pwr-up ramp rate . . . . . . . 5.75v, 1v/s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v current into in+, in-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v - -0.5v to v + +0.5v esd tolerance human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v thermal resistance ja (c/w) 6 ld sot package . . . . . . . . . . . . . . . . . . . . . . . . . 230 6 ld wlcsp package . . . . . . . . . . . . . . . . . . . . . . . 130 8 ld soic package . . . . . . . . . . . . . . . . . . . . . . . . 125 ambient operating temperature range . . . . . . . . .-40c to +125c storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v + = 5v, v - = 0v, v cm = 2.5v, v o = 2.5v, t a = +25c unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c parameter description test conditions min (note 4) typ max (note 4) unit v os input offset voltage sot-23 -1 0.05 +1 mv -1.5 +1.5 mv wlcsp -1.5 +1.5 mv long term input offset voltage stability 3 v/mo input offset drift vs temperature 1.1 v/c i b input bias current (see figure 20) -25 1 25 pa -600 600 pa e n input noise voltage peak-to-peak f = 0.1hz to 10hz 2.8 v p-p input noise voltage density f o = 1khz 48 nv/ hz i n input noise current density f o = 1khz 0.15 pa/ hz cmir input voltage range guaranteed by cmrr test 0 5 v cmrr common-mode rejection ratio v cm = 0v to 5v 80 100 db 75 db psrr power supply rejection ratio v s = 2.4v to 5.5v 80 100 db 80 db a vol large signal voltage gain v o = 0.5v to 4.5v, r l = 100k to (v + + v - )/2 100 400 v/mv 100 v/mv v out maximum output voltage swing sot-23 v ol ; output low, r l = 100k to (v + + v - )/2 3 10 mv v ol ; output low, r l = 1k to (v + + v - )/2 130 250 mv 350 mv v oh ; output high, r l = 100k to (v + + v - )/2 4.994 4.9975 v 4.994 v v oh ; output high, r l = 1k to (v + + v - )/2 4.750 4.875 v 4.7 v v os time ------------------ v os t --------------- - el8188
3 fn7467.7 february 24, 2011 v out maximum output voltage swing wlcsp v ol ; output low, r l = 100k to (v+ + v-)/2 3 10 mv v ol ; output low, r l = 1k to (v+ + v-)/2 130 250 mv 350 mv v oh ; output high, r l = 100k to (v+ + v-)/2 4.991 4.997 v v oh ; output high, r l = 1k to (v+ + v-)/2 4.750 4.875 v 4.7 v sr slew rate 0.1 0.15 0.19 v/s 0.07 0.25 v/s gbwp gain bandwidth product f o = 100khz 266 khz i s, on supply current, enabled sot-23 35 55 75 a 30 85 a wlcsp 456585a 40 95 a i sc + short circuit output current r l = 10 to opposite supply 23 31 ma 18 ma i sc - short circuit output current r l = 10 to opposite supply 20 26 ma 15 ma v s supply voltage guaranteed by psrr 2.4 5.5 v 2.4 5.5 v note: 4. . compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v + = 5v, v - = 0v, v cm = 2.5v, v o = 2.5v, t a = +25c unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c (continued) parameter description test conditions min (note 4) typ max (note 4) unit el8188
4 fn7467.7 february 24, 2011 typical performance curves v s = 2.5v, t a = +25c, unless otherwise specified figure 1. unity gain frequency response at various supply voltages figure 2. frequency response at various closed loop gains figure 3. supply current vs supply voltage figure 4. input offset voltage vs output voltage figure 5. input offset voltage vs common-mode input voltage figure 6. open loop gain and phase vs frequency (r l = 1k ) -3 -2 -1 0 1 1k 10k 100k 1m v s = 1.0 v s = 2.5 v s = 1.2 gain (db) frequency (hz) r l 10k v out = 0.2v p-p -20 -10 0 10 20 30 40 50 60 70 80 1 10 100 1k 10k 100k 1m 10m frequency (hz) gain (db) gain = 200 gain = 1k gain = 500 gain = 100 gain = 10 gain = 1 gain = 5 gain = 2 r l 10k v out = 0.2v p-p 2.0 3.0 4.0 5.5 0 supply voltage (v) supply current (a) 2.5 10 20 50 60 30 40 3.5 5.0 4.5 -0.5 5.5 -200 output voltage (v) input offset voltage (v) -100 0 200 100 0.5 1.5 2.5 3.5 4.5 a v = -1 v cm = v dd /2 -0.5 5.5 -250 common-mode input voltage (v) normalized input offset voltage (v) -150 -50 250 150 0.5 1.5 2.5 3.5 4.5 50 -20 gain (db) 0 20 80 100 40 60 10 10 k 1m frequency (hz) 100 phase shift () 0 45 90 135 180 100 k 1 k phase gain el8188
5 fn7467.7 february 24, 2011 figure 7. open loop gain and phase vs frequency (r l = 100k ) figure 8. cmrr vs frequency figure 9. psrr vs frequency figure 10. input voltag e and current noise vs frequency figure 11. 0.1hz to 10hz input voltage noise figure 12. vos drift (sot-23 package) vs time typical performance curves (continued) v s = 2.5v, t a = +25c, unless otherwise specified (continued) -10 0 10 20 30 40 50 60 70 80 90 100 10 100 1k 10k 100k 1m frequency (hz) gain (db) 180 135 90 gain phase phase shift () -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 10 frequency (hz) cmrr (db) 0 v cm = 1v p-p r l = 100k 10 100 1k 10k 100k 1m a v = +1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1k 10k 100k frequency (hz) psrr (db) +psrr -psrr v s = 1v p-p r l = 100k a v = +1 1m 1 10 100 1000 1 10 100 1k 10k 100k frequency (hz) voltage noise ( v) 0.1 1 10 100 current noise (pa/ hz) current voltage time (1s/div) voltage noise (500nv/div) 2.8v p-p -15 -10 -5 0 5 10 15 20 0 500 1000 1500 time (hours) vos drift (v) 1800 el8188
6 fn7467.7 february 24, 2011 figure 13. sot-23 supply current vs temperature, v s = 2.5v figure 14. wlcsp supply current vs temperature, v s = 2.5v figure 15. sot-23 v os vs temperature, v s = 2.5v figure 16. sot-23 v os vs temperature, v s = 1.2v figure 17. wlcsp v os vs temperature, v s = 2.5v figure 18. wlcsp v os vs temperature, v s = 1.2v typical performance curves (continued) v s = 2.5v, t a = +25c, unless otherwise specified (continued) 35 40 45 50 55 60 65 70 75 -40 -20 0 20 40 60 80 100 120 temperature (c) current (ma) median min max n = 1500 45 50 55 60 65 70 75 80 85 -40-200 20406080100120 temperature (c) current (a) median min max n = 5000 -400 -300 -200 -100 0 100 200 300 400 -40 -20 0 20 40 60 80 100 120 temperature (c) vos ( v) median min max n = 1500 -800 -600 -400 -200 0 200 400 600 800 vos ( v) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 -40-200 20406080100120 temperature (c) v os (v) 1500 1000 500 0 -500 -1000 -1500 median min max n = 5000 -1500 -1000 -500 0 500 1000 1500 -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 5000 v os (v) el8188
7 fn7467.7 february 24, 2011 figure 19. i bias+ vs temperature, v s = 2.5v figure 20. i bias- vs temperature, v s = 2.5v figure 21. cmrr vs temperature, v+ = 2.5v, 1.5v figure 22. psrr vs temperature 1.5v to 2.5v figure 23. v out high vs temperature, v s = 2.5v, r l =1k figure 24. v out high vs temperature, v s = 2.5v, r l =100k typical performance curves (continued) v s = 2.5v, t a = +25c, unless otherwise specified (continued) -20 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 100 120 temperature (c) ibias + (pa) median min max n = 1500 -10 10 30 50 70 90 110 130 150 170 190 210 230 250 -40 -20 0 20 40 60 80 100 120 temperature (c) ibias -(pa) median min max n = 1500 80 85 90 95 100 105 110 115 120 125 130 cmrr (db) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 85 90 95 100 105 110 115 120 125 130 psrr (db) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 4.84 4.85 4.86 4.87 4.88 4.89 4.90 v out (v) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 4.9964 4.9966 4.9968 4.9970 4.9972 4.9974 4.9976 4.9978 4.9980 4.9982 4.9984 v out (v) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 el8188
8 fn7467.7 february 24, 2011 figure 25. v out low vs temperature, v s = 2.5v, r l =1k figure 26. v out low vs temperature, v s = 2.5v, r l =100k figure 27. a vol vs temperature, r l = 100k, v o = 2v @ v s = 2.5v typical performance curves (continued) v s = 2.5v, t a = +25c, unless otherwise specified (continued) 100 110 120 130 140 150 160 170 180 190 v out (mv) -40-200 20406080100120 temperature (c) median min max n = 1500 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v out (mv) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 160 210 260 310 360 410 460 510 a vol (v/mv) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max n = 1500 el8188
9 fn7467.7 february 24, 2011 application information introduction the el8188 is a rail-to-rail input and output (rrio), micro-power, precision, single supply op amp. this amplifier is designed to operate from single supply (2.4v to 5.5v) or dual supply ( 1.2v to 2.75v) while drawing only 55a of supply current.the device achieves rail-to-rail input and output operation while eliminat ing the drawbacks of many conventional rrio op amps. rail-to-rail input the pfet input stage of the el8188 has an input common-mode voltage range that includes the negative and positive supplies without in troducing offset errors or degrading performance like some existing rail-to-rail input op amps. many rail-to-rail input st ages use two differential input pairs: a long-tail pnp (or pfet) and an npn (or nfet). severe penalties result from using this topology. as the input signal moves from one supply rail to the other, the op amp switches from one input pair to the other causing changes in input offset voltage and an undesired change in the input offset current?s magnitude and polarity. the el8188 achieves rail-to-rail input performance without sacrificing important precision specifications and without degrading distortion performance. the el8188's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. rail-to-rail output a pair of complementary mosfet devices achieves rail-to-rail output swing. the nmos sinks cu rrent to swing the output in the negative direction, while the pmos sources current to swing the output in the positiv e direction. the el8188 with a 100k load swings to within 3mv of the supply rails. results of over-driving the output caution should be used when over-driving the output for long periods of time. over-driving the output can occur in three ways: 1. the input voltage times the gain of the amplifier exceeds the supply voltage by a large value. 2. the output current required is higher than the output stage can deliver. 3. operating the device in slew rate limit. these conditions can result in a shift in the input offset voltage (vos) as much as 1v/hr of exposer under these condition. in+ and in- input protection in addition to esd protection diodes to each supply rail, the el8188 has additional back-to-ba ck protection diodes across the differential input terminals (see ?circuit 1? diagram on page 8). if the magnitude of the differential input voltage exceeds the diode?s v f , then one of these diodes will conduct. for elevated temperatures, the leakage of the protection diodes (circuit 1 pin description table) increases, resulting in the increase in ibias as seen in figures 19 and 20. usage implications if the input differential voltage is expected to exceed 0.5v, an external current limiting resistor must be used to ensure the input current never exceeds 5ma. for noninverting unity gain applications the current limiting can be via a series in+ resistor, or via a feedback resistor of appropriate value. for other gain configurations, the series in+ resi stor is the best choice, unless the feedback (r f ) and gain setting (r g ) resistors are both sufficiently large to limit the input current to 5ma. pin descriptions 8 ld soic pin number sot-23 pin number 6 ld wlcsp pin number pin name equivalent circuit description 1, 5 dnc do not connect; internal connection - must be left floating. 2 4 c1 in- circuit 1 amplifier?s inverting input 3 3 c2 in+ circuit 1 amplifier?s non-inverting input 4 2 b2 v- circuit 3 negative power supply 8 5 a1 dnc do not connect. pin must be left floating. 6 1 a2 out circuit 2 amplifier?s output 7 6 b1 v+ circuit 3 positive power supply out circuit 3 circuit 2 capacitively coupled esd clamp v + v + v - v - in- v + v - circuit 1 in+ el8188
10 fn7467.7 february 24, 2011 large differential input voltages can arise from several sources: 1) during open loop (comparator) operation. the in+ and in- input voltages don?t track. 2) when the amplifier is disabled but an input signal is still present. an r l or r g to gnd keeps the in- at gnd, while the varying in+ signal creates a differential voltage. mux amp applications are similar, e xcept that the active channel v out determines the voltage on the in- terminal. 3) when the slew rate of the input pulse is considerably faster than the op amp?s slew rate. if the v out can?t keep up with the in+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. to avoid this issue, keep the input slew rate below 0.2v/s, or use appropriate current limiting resistors. output current limiting the el8188 has no internal current-limiting circuitry. if the output is shorted, it is po ssible to exceed the ?absolute maximum rating? for ?operating junction temperature?, potentially resulting in the destruction of the device. power dissipation it is possible to exceed the +150c maximum junction temperature (t jmax ) under certain load and power-supply conditions. it is therefore important to calculate t jmax for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these parameters are related as follows: where pd max is calculated using: where: ?t max = maximum ambi ent temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of the amplifier ?v s = supply voltage ?i max = maximum supply current of the amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance proper layout maximizes precision to achieve the optimum levels of high input impedance (i.e., low input currents) and low offset voltage, care should be taken in the circuit board layout. the pc board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. when input leakage current is a paramount concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. figure 28 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. the guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. for further reduction of leakage currents, mount components to the pc board using teflon standoffs. typical applications a general-purpose combination ph probe has extremely high output impedance typically in the range of 10g to 12g . low loss and expensive teflon cables are often used to connect the ph probe to the meter electronics. figure 29 details a low-cost alternative solution using the el8188 and a low-cost coax cable. the el8188 pmos high impedance input senses the ph probe output signal and buffers it to drive the coax cable. its rail-to-rail input nature also eliminates the need for a bias resistor network required by other amplifiers in the same application. t jmax t max ja pd max () + = (eq. 1) pd max v s i smax v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2) in v+ figure 28. guard ring example for unity gain amplifier high impedance input - + 3v + v + v - el8188 coax general purpose combination ph probe figure 29. ph probe amplifier el8188
11 fn7467.7 february 24, 2011 thermocouples are the most popular temperature sensing devices because of their low cost, interchangeability, and ability to measure a wide range of temperatures. in figure 30, the el8188 converts the differential thermocouple voltage into single-ended signal with 10x gain. the el8188's rail-to-rail input characteristic allows the thermocouple to be biased at ground and permits the op amp to operate from a single 5v supply. - + 5v + v + v - el8188 k type thermocouple 10k r 3 10k r 2 r 4 100k r 1 100k 410v/c figure 30. thermocouple amplifier el8188
12 fn7467.7 february 24, 2011 el8188 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?
13 fn7467.7 february 24, 2011 el8188 package outline drawing p6.064a 6 lead small outline transistor plastic package rev 0, 2/10 1.60 0.08-0.20 see detail x (0.60) 0-3 3 5 detail "x" side view typical recommended land pattern top view end view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 1.45 max c b a d 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 64 5 5 13 2 plane dimension is exclusive of mold flash, protrusions or gate burrs. this dimension is measured at datum ?h?. package conforms to jedec mo-178aa. foot length is measured at reference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7467.7 february 24, 2011 el8188 wafer level chip scale package (wlcsp) pin 1 id a e1 bottom view cb a b d 1 side view a 1 a 2 top view d e sd 2 1 e se b w3x2.6c 3x2 array 6 ball wafer level chip scale package symbol millimeters a 0.51 min, 0.55 max a 1 0.225 0.015 a 2 0.305 0.013 b 0.323 0.025 d 0.955 0.020 d 1 0.50 basic e 1.455 0.020 e 1 1.00 basic e 0.50 basic sd 0.25 basic se 0.00 basic rev. 3 03/08 notes: 1. all dimensions are in millimeters.

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